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FEATURES Composite Video Output Chrominance and Luminance (S-Video) Outputs No External Filters or Delay Lines Required Drives 75 Reverse-Terminated Loads Compact 28-Pin PLCC Logic Selectable NTSC or PAL Encoding Modes Automatically Selects Proper Chrominance Filter Cutoff Frequency for Encoding Standard Logic Selectable Encode or Power-Down Mode (AD720 Only) Logic Selectable Encode or Bypass Mode (AD721 Only) Low Power: 200 mW typical APPLICATIONS RGB to NTSC or PAL Encoding Drive RGB Signals into 75 Load (AD721 Only) PRODUCT DESCRIPTION
RGB to NTSC/PAL Encoders AD720/AD721
(subcarrier amplitude and phase) signals in accordance with either NTSC or PAL standards. These two outputs are also combined to provide a composite video output. All three outputs are available separately at voltages of twice the standard signal levels as required for driving 75 reverse terminated cables. The AD721 also features a bypass mode, in which the RGB inputs may bypass the encoder section of the IC via three gain-of-two amplifiers suitable for driving 75 reverse terminated cables. The AD720 and AD721 provide a complete, fully calibrated function, requiring only termination resistors, bypass capacitors, a clock input at four times the subcarrier frequency, and a composite sync pulse. There are two control inputs: one input selects the TV standard (NTSC/PAL) and the other (ENCD) powers down most sections of the chip when the encoding function is not in use (AD720) or activates the triple bypass buffer to drive the RGB signals when RGB encoding is not required (AD721). All logical inputs are CMOS compatible. The chip operates from 5 V supplies. (continued on page 5)
The AD720 and AD721 RGB to NTSC/PAL Encoders convert red, green and blue color component signals into their corresponding luminance (baseband amplitude) and chrominance
FUNCTIONAL BLOCK DIAGRAM
NTSC/PAL ASNC C-SYNC SYNC DECODER C-SYNC DELAY BURST 180 (PAL ONLY) SC 90/270 NTSC/PAL CLOCK AT 8FSC DELAYED C-SYNC NTSC/PAL
POWER AND GROUNDS
+5V +5V -5V AGND DGND LOGIC ANALOG ANALOG ONLY ANALOG LOGIC
SC 90 4FSC ENCD QUADRATURE DECODER SC 0 BURST Y
RED
5MHz 4-POLE LP PRE-FILTER 1.2MHz 4-POLE LPF 1.2MHz 4-POLE LPF
SAMPLEDDATA DELAY LINE
DC RESTORE AND C-SYNC INSERTION NTSC/PAL
5MHz 2-POLE LP POSTFILTER
LUMINANCE OUTPUT*
X2 -0.572V TO 1.43V NTSC -0.6V TO 1.4V PAL
GREEN
RGB-TO-YUV ENCODING MATRIX
U
COMPOSITE OUTPUT*
X2 -0.572V TO 2V NTSC -0.6V TO 2V PAL
V BLUE
BALANCED MODULATORS
3.6MHz (NTSC) 4.4MHz (PAL) 3-POLE LPF
X2
CHROMINANCE OUTPUT*
572mVp-p NTSC 600mVp-p PAL
X2
ROUT
1.5Vp-p
AD721
(ONLY)
X2
GOUT
1.5Vp-p
*NOTE: THE LUMINANCE, COMPOSITE, AND CHROMINANCE OUTPUTS ARE AT TWICE NORMAL LEVELS FOR DRIVING 75 REVERSE-TERMINATED LINES.
X2
BOUT
1.5Vp-p
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD720/AD721-SPECIFICATIONS
Parameter SIGNAL INPUTS (RDIN, GRIN, BLIN) Input Amplitude Input Resistances1 RDIN with Respect to AGND GRIN with Respect to AGND BLIN with Respect to AGND Input Capacitance LOGIC INPUTS (C-SYNC, 4FSC, ENCD, NTSC) Logic LO Input Voltage Logic HI Input Voltage Logic LO Input Current (DC) Logic HI Input Current (DC) BYPASS AMPLIFIERS (AD721 Only) Gain Error Small Signal -3 dB Bandwidth Output Offset Voltage (Active State) Output Voltage (Inactive State) VIDEO OUTPUTS3 (LUMA, CRMA, CMPS) Luminance (LUMA) Output Bandwidth Gain Error Linearity Sync Level Chrominance (CRMA) Output Bandwidth Color Burst Amplitude Absolute Gain Error Absolute Phase Error Chroma/Luma Time Alignment4 Composite Output Absolute Gain Error Differential Gain Differential Phase Output Offset Voltage Chroma Feedthrough POWER SUPPLIES (APOS, DPOS, VNEG) Recommended Supply Range Full Output Current5 Zero Signal Quiescent Current Bypass Mode Quiescent Current (AD721 Only) NTSC PAL
(TA = +25C and supplies = 5 V unless otherwise noted)
Min Typ 714 700 2.3 4.2 4.2 5 1 4 <1 <1 Max Unit mV mV k k k pF V V A A % MHz mV mV
Conditions
Nominal Gain of x22
-5 100 -50 -50
+5 +50 +50
-5 NTSC PAL NTSC PAL NTSC PAL 252
5 1 0.1 286 300
+5 320
MHz % % mV mV MHz MHz mV p-p mV p-p % Degrees ns % % Degrees mV mV p-p V mA mA mA mA mA mA
257 -15
NTSC -5 With Respect to Chroma Channel With Respect to Chroma Channel Chroma, Luma, or Composite Outputs Monochrome Input Dual Supply -5 V Supply +5 V Supply -5 V Supply +5 V Supply -5 V Supply +5 V Supply 4.75
3.6 4.4 286 315 300 5 +15 3 -170 1 0.1 0.1 50 20 +5
100 55 5.25
10 10
35 67 20 20 14 14
35 35 20 20
NOTES 1 Input scaling resistors provide best scaling accuracy when source resistance is 37.5 (75 reverse-terminated input). 2 Required for driving a 75 double reverse terminated load. 3 All outputs are measured at a reverse-terminated load; voltages at IC pins are twice those specified here. 4 This is a predistortion (per FCC specifications) that compensates for the chroma/luma delay in the low-pass filter that separates the luminance and chrominance signals in a television receiver. 5 CRMA, LUMA, and CMPS outputs are all connected to 75 reverse-terminated loads; full-white signal for entire field. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. Specifications subject to change without notice.
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AD720/AD721
Supply Voltage VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 600 mW Operating Temperature Range . . . . . . . . . . . . . . 0C to +70C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature, Soldering 60 sec . . . . . . . . . . . . . . +300C
NOTE *Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended rating conditions for extended periods may affect device reliability. Thermal characteristics: 28-pin plastic package: JA = 100C.
ABSOLUTE MAXIMUM RATINGS*
PIN DESCRIPTIONS
Pin Mnemonic*
1 2 3 4 5 (NC) GOUT (NC) APOS (NC) ROUT AGND ENCD
Description*
(No Connection) Green Bypass Buffer (No Connection) Analog Positive Supply; +5 V 5% (No Connection) Red Bypass Buffer Analog Ground Connection A Logical High Enables the NTSC/PAL Encode Mode (A Logical Low Powers Down the Chip) A Logical Low Enables the RGB Bypass Mode Red Component Video Input 0 mV to 714 mV for NTSC 0 mV to 700 mV for PAL Analog Ground Connection Green Component Video Input 0 mV to 714 mV for NTSC 0 mV to 700 mV for PAL Analog Ground Connection Blue Component Video Input 0 mV to 714 mV for NTSC 0 mV to 700 mV for PAL A Logical High Input Selects NTSC Encoding A Logical Low Input Selects PAL Encoding CMOS Logic Levels Analog Ground Connection Chrominance Output; Subcarrier Only** 572 mV Peak-to-Peak for NTSC 600 mV Peak-to-Peak for PAL Analog Positive Supply; +5 V 5% Composite Video Output** -572 mV to 2 V for NTSC -600 mV to 2 V for PAL Analog Positive Supply; +5 V 5% Luminance Plus SYNC Output** -572 mV to 1.43 V for NTSC -600 mV to 1.4 V for PAL System Negative Supply; -5 V 5% Digital Ground Connection Clock Input at Four Times the Subcarrier Frequency 14.318 180 MHz for NTSC 17.734 480 MHz for PAL CMOS Logic Levels Digital Positive Supply; +5 V 5% A Logical High Input Resets the Subcarrier Phase Every Frame A Logical Low Input Resets the Subcarrier Phase Every Fourth Frame CMOS Logic Levels Digital Positive Supply; +5 V 5% Input for Composite Television Synchronization Pulses Negative Sync Pulses CMOS Logic Levels Digital Ground Connections (One of Two) System Negative Supply; -5 V 5% (No Connection) Blue Bypass Buffer Analog Positive Supply; +5 V 5%
6
RDIN
7 8
AGND GRIN
ORDERING GUIDE
Model AD720JP AD721JP
Temperature Range 0C to +70C 0C to +70C
Package 28-Pin PLCC 28-Pin PLCC
Package Option P-28A P-28A
9 10
AGND BLIN
11
STND
PIN CONNECTIONS 28-Lead Plastic Leaded Chip Carrier (PLCC) Package P-28A
GOUT (NC) ROUT (NC) APOS (NC) BOUT (NC)
12 13
AGND CRMA
14 15
VNEG
APOS CMPS
AGND
APOS
4
3
2
1
28
27
26
16 17
25 DGND 24 SYNC
APOS LUMA
ENCD RDIN AGND GRIN AGND
5 6 7 8 9
AD720/AD721 RGB TO NTSC/PAL ENCODER
23 DPOS 22 ASNC
18 19 20
VNEG DGND 4FSC
21 DPOS 20 4FSC 19 DGND
BLIN 10 STND 11
21 22
DPOS ASNC
12
AGND
13
CRMA
14
APOS
15
CMPS
16
APOS
17
LUMA
18
VNEG
23 24
DPOS SYNC
NOTE: CONNECTIONS IN ( ) PERTAIN ONLY TO AD720
25 26 27 28
DGND VNEG (NC) BOUT APOS
*( ) pertain only to AD720. **The luminance, chrominance, and composite outputs are at twice normal levels for driving 75 reverse-terminated lines.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD720/AD721 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD720/AD721-Typical Characteristics
COMPOSITE VIDEO COMPOSITE SYNC RGB 3 75 4FSC TEKTRONIX 1910 COMPOSITE VIDEO WAVEFORM GENERATOR FSC PIXEL-CLOCK GENERATOR TEKTRONIX VM700A WAVEFORM MONITOR
0.0 VOLTS IRE:FLT
TEKTRONIX TSG 300 COMPONENT VIDEO WAVEFORM GENERATOR
AD720/AD721 RGB TO NTSC/PAL ENCODER
SONY MONITOR MODEL 1342
FRAMES SELECTED: 1 2; APL = 45.8% 525 LINE NTSC; NO FILTERING SLOW CLAMP TO 0.00V AT 6.63s PRECISION MODE OFF SYNC = SOURCE
100.0
GENLOCK
75
0.5 50.0
Figure 1. AD720/AD721 Evaluation Setup
DG DP(NTSC) (SYNC = EXT) FIELD = 1 LINE = 21 DIFFERENTIAL GAIN (%) MIN = -0.10; MAX = 0.00; p-p/MAX = 0.10 0.00 0.10 0.05 0.00 -0.05 -0.10 DIFFERENTIAL PHASE () MIN = 0.00; MAX = 0.07; p-p = 0.07 0.07 0.01 0.00 0.05 0.05 0.04 0.10 0.05 0.00 -0.05 -0.10 1ST 2ND 3RD 4TH 5TH 6TH
0.0 0.5 50.0 VOLTS IRE:FLT FRAMES SELECTED: 1 2; APL = 11.3% 525 LINE NTSC; NO FILTERING SLOW CLAMP TO 0.00V AT 6.63s PRECISION MODE OFF SYNC = SOURCE
0.0
10.0
20.0
30.0 40.0 MICROSECONDS
50.0
60.0
70.0
-0.04
0.00
-0.01
-0.04
-0.10
Figure 4. 100% Color Bars, NTSC
100.0
Figure 2. Composite Output Differential Phase and Gain, NTSC (Nulled to Chroma Output)
VOLTS IRE:FLT NOISE REDUCTION: 15.05dB APL = 49.6% 525 LINE NTSC; NO FILTERING SLOW CLAMP TO 0.00V AT 6.63s SYNC = SOURCE FRAMES SELECTED: 1 2 0.0 10.0 10.0 20.0 30.0 40.0 MICROSECONDS 50.0 60.0 70.0
Figure 5. Multipulse, NTSC
H TIMING MEASUREMENT RS-170A (NTSC) FIELD = 1 LINE = 22 8.0 CYCLES 5.35s
100.0
0.5 50.0
4.82s
0.0
85ns 39.4 IRE 73ns
0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0
39.2 IRE
MICROSECONDS/PRECISION MODE OFF
AVERAGE 32 TO 32
Figure 3. Modulated Pulse and Bar, NTSC
H TIMING (PAL) LINE = 17 5.52s 4.82s 81ns 302.2mV 82ns AVERAGE 32 TO 32
Figure 6. Horizontal Timing, NTSC
1.98s
292.1mV
Figure 7. Horizontal Timing, PAL
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AD720/AD721
(continued from page 1) All required low-pass filters are on chip. After the input signals pass through a precision RGB to YUV encoding matrix, two onchip low-pass filters limit the bandwidth of the U and V color difference signals to 1.2 MHz prior to quadrature modulation of the color subcarrier; a third low-pass filter at 3.6 MHz (NTSC) or 4.4 MHz (PAL) follows the modulators to limit the harmonic content of the output. Delays in the U and V chroma filters are matched by an on-chip sampled data delay line in the Y signal path; to prevent aliasing, prefilter at 5 MHz is included ahead of the delay line and a post filter at 5 MHz is added after the delay line to suppress harmonics in the output. These low-pass filters are optimized for minimum pulse overshoot. The overall delay is about 170 ns, which precompensates for delays in the filters used to decode the NTSC or PAL signal in a television receiver. (This precompensation delay is already present in TV broadcasts.) The AD720 and AD721 are available in a 28-pin plastic leaded chip carrier for the 0C to +70C commercial temperature range.
THEORY OF OPERATION
Y = 0.299R + 0.587G + 0.114B U = 0.493 (B-Y) V = 0.877 (R-Y) For NTSC operation, the chroma amplitude is increased by the factor 1.06 prior to summation with the luminance output. The burst signal is inserted into the Y channel in the encoding matrix. The three outputs of the encoding matrix, now transformed into Y, U, and V components, take two paths. The Y (luminance) signal is passed through a delay line consisting of a prefilter, a sampled-data delay line, and a post filter. The pre- and post-filters prevent aliasing of harmonics back into the baseband video. The overall delay is a nominal -170 ns relative to the chrominance signal, in keeping with broadcast requirements to compensate for delays introduced by the filters in the decoding process. The U and V components pass through 4-pole modified Bessel low-pass filters with a 1.2 MHz -3 dB frequency to prevent aliasing in the balanced modulators, where they modulate a 3.579 545 000 MHz (NTSC) or 4.433 618 750 MHz (PAL) signal via a pair of balanced modulators driven in quadrature by the color subcarrier. The AD720/AD721 4FSC input drives a digital divide-by-4 circuit (two flip-flops) to create the quadrature signal. The reference phase 0 is used for the U signal. In the NTSC mode, the V signal is modulated at 90, but in the PAL mode, the V modulation input alternates between 90 and 270 at half the line rate as required by the PAL standard. The outputs of the balanced modulators are summed and low-pass filtered to remove harmonics.
Referring to the AD720/AD721 block diagram (Figure 8), the RGB inputs (each 0 mV to 714 mV in NTSC or 0 mV to 700 mV in PAL) are first encoded into luminance and color difference signals. The luminance signal is called the "Y" signal and the color-difference signals are called U and V. The RGB inputs are encoded into the YUV format using the transformation
NTSC/PAL ASNC C-SYNC SYNC DECODER
C-SYNC DELAY BURST
DELAYED C-SYNC NTSC/PAL
POWER AND GROUNDS
+5V +5V LOGIC ANALOG ANALOG ONLY ANALOG LOGIC
SC 90 4FSC ENCD QUADRATURE DECODER SC 0 BURST Y
180 (PAL ONLY)
SC 90/270 NTSC/PAL CLOCK AT 8FSC
-5V AGND DGND
RED
5MHz 4-POLE LP PRE-FILTER 1.2MHz 4-POLE LPF 1.2MHz 4-POLE LPF
SAMPLEDDATA DELAY LINE
DC RESTORE AND C-SYNC INSERTION NTSC/PAL
5MHz 2-POLE LP POSTFILTER
LUMINANCE OUTPUT*
X2 -0.572V TO 1.43V NTSC -0.6V TO 1.4V PAL
GREEN
RGB-TO-YUV ENCODING MATRIX
U
COMPOSITE OUTPUT*
X2 -0.572V TO 2V NTSC -0.6V TO 2V PAL
V BLUE
BALANCED MODULATORS
3.6MHz (NTSC) 4.4MHz (PAL) 3-POLE LPF
X2
CHROMINANCE OUTPUT*
572mVp-p NTSC 600mVp-p PAL
X2
ROUT
1.5Vp-p
AD721
(ONLY)
*NOTE: THE LUMINANCE, COMPOSITE, AND CHROMINANCE OUTPUTS ARE AT TWICE NORMAL LEVELS FOR DRIVING 75 REVERSE-TERMINATED LINES.
X2
GOUT
1.5Vp-p
X2
BOUT
1.5Vp-p
Figure 8. AD720/AD721 Functional Block Diagram
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-5-
AD720/AD721
The filtered output is summed with the luminance signal to create a composite video signal. The separate luminance, chrominance, and composite video signals are amplified by gain-of-two amplifiers for driving 75 reverse-terminated lines. The separate luminance and chrominance outputs together are known as "S-Video." The digital section of the AD720/AD721 is clocked by the 4FSC input. It measures the width of pulses in the composite sync input to separate vertical, horizontal, and serration pulses and to insert the subcarrier burst only after a valid horizontal sync pulse.
+5V FROM ANALOG SUPPLY 0.1F
Asserting the ENCD pin to a logical low routes the AD721's RGB inputs through three gain-of-two bypass buffers for driving 75 reverse-terminated lines, bypassing the encoder section of the AD721. The triple bypass amplifier is utilized to overcome the loading effects of a "TV-out" connection on the RGB monitor output. When a video encoder is connected to outputs of a current-out video RAMDAC or VGA controller, the R, G, and B signals to the monitor are loaded-down. This requires the use of a gain block to properly drive the monitor.
0.1F
-5V FROM ANALOG SUPPLY
AGND 5 ENCD RDIN AGND
APOS
ENCODE INPUT ENCODE = CMOS HIGH POWER DOWN = CMOS LOW
4
3
2
1
28
27
26 VNEG DGND 25 SYNC 24 DPOS 23 COMPOSITE SYNC INPUT CMOS LOGIC LEVEL NEGATIVE SYNC TIPS 0.1F ASNC 22 +5V FROM DIGITAL SUPPLY +5V FROM DIGITAL SUPPLY
NC
NC
NC
IOR 75 75
6 7
VIDEO RAM-DAC
ADV47X ADV71XX IOG 75 75
AD720
8 9 GRIN AGND
RGB TO NTSC/PAL ENCODER
NC
DPOS 21 0.1F 4FSC 20 DGND 19 VNEG 18
IOB 75 VIDEO STANDARD SELECTION INPUT NTSC = CMOS HIGH PAL = CMOS LOW 75
10 BLIN
11 STND AGND 12
0.1F
4 X SUBCARRIER INPUT CMOS LOGIC LEVELS NTCS = 14.318 180MHz PAL = 17.734 480MHz
CRMA
APOS
CMPS
APOS
16
13
14
15
17
LUMA
-5V FROM ANALOG SUPPLY 75 +5V FROM ANALOG SUPPLY 0.1F LUMINANCE OUTPUT 75 COMPOSITE OUTPUT 75 CHROMINANCE OUTPUT
Figure 9. AD720 Application
75 RED OUTPUT 75 0.1F +5V FROM 75 ANALOG SUPPLY 0.1F 4 ENCODE INPUT ENCODE = CMOS HIGH BYPASS = CMOS LOW IOR 75 75 7 8 75 75 9 IOB 75 VIDEO STANDARD SELECTION INPUT NTSC = CMOS HIGH PAL = CMOS LOW 75 11 STND AGND 12 DGND 19 VNEG 18 -5V FROM ANALOG SUPPLY 75 +5V FROM ANALOG SUPPLY 0.1F LUMINANCE OUTPUT 75 COMPOSITE OUTPUT 75 CHROMINANCE OUTPUT 0.1F 4 X SUBCARRIER INPUT CMOS LOGIC LEVELS NTCS = 14.318 180MHz PAL = 17.734 480MHz AGND AGND DPOS 23 AGND 5 6 ENCD RDIN 3 2 1 28 27 26 VNEG DGND 25 SYNC 24 COMPOSITE SYNC INPUT CMOS LOGIC LEVEL NEGATIVE SYNC TIPS 0.1F ASNC 22 DPOS 21 0.1F 10 BLIN 4FSC 20 +5V FROM DIGITAL SUPPLY +5V FROM DIGITAL SUPPLY GREEN OUTPUT BLUE OUTPUT -5V FROM ANALOG SUPPLY
NC
NC
NC
VIDEO RAM-DAC
ADV47X IOG ADV71XX
AD721
GRIN
RGB TO NTSC/PAL ENCODER
CRMA
APOS
CMPS
APOS
16
APOS
13
14
15
17
Figure 10. AD721 Application
LUMA
NC
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AD720/AD721
APPLYING THE AD720/AD721
Figure 9 shows the application of the AD720 and Figure 10 shows the application of the AD721. Note that the AD720 and AD721 differ from other analog encoders because they are dc coupled. This means that, for example, the expected RGB inputs are 0 mV to 714 mV in NTSC and 0 mV to 700 mV in PAL. The luminance, chrominance, and composite outputs are also dc coupled. These outputs can drive a 75 reverseterminated load. Unused outputs should be terminated with 150 resistors. The RGB data must be supplied to the AD720/AD721 at NTSC or PAL rates, interlaced format. Various VGA chip set vendors support this mode of operation. Most computers supply RGB outputs in noninterlaced format at higher data rates than NTSC and PAL, which means that "outboard" encoders must supply some form of timing conversion before the RGB data reaches the AD720/AD721. Note also that the AD720/AD721 does not have internal dc restoration and does not accept sync on green. The composite sync input is a separate, CMOS logical-level input and must be synchronized with the 4FSC input, which serves as the master clock for the AD720/AD721. The AD720/AD721 does not implement two elements of the PAL and NTSC standards. In NTSC operation, it does not support the 7.5 IRE unit setup (1 IRE unit = 7.14 mV)--this must be added via software using the RGB inputs. Many RAMDACs, such as the Analog Devices ADV471 and ADV478, offer a logic-selectable setup mode. In PAL operation, the AD720/ AD721 does not implement a 25 Hz subcarrier offset.
Decoupling and Grounding
separator in the AD720/AD721 ignores horizontal sync pulses that are too long or too short. Figure 11 shows the timing windows for valid NTSC and PAL horizontal sync pulses.
NTSC: 5.30s PAL: 5.46s COLOR BURST
COMPOSITE SYNC PULSE
NTSC: 2.79s PAL: 3.21s
NTSC: 2.51s PAL: 2.25s
NTSC: 2.51s PAL: 2.25s
IF THE TRAILING EDGE OF A COMPOSITE SYNC PULSE IS WITHIN THIS WINDOW, THE PULSE IS TREATED AS A HORIZONTAL SYNC PULSE. IF THE TRAILING EDGE IS OUTSIDE THIS WINDOW, THE PULSE IS TREATED AS AN EQUALIZING OR BLANKING PULSE.
Figure 11. NTSC and PAL Timing for Valid Horizontal Sync Pulses
When the horizontal sync pulses are too long or too short, a dc offset voltage (due to charge storage) increases on the output of the sampled data delay line's auto-zero amplifier. Normally, this offset voltage is removed at the beginning of every line, as signified by the horizontal sync pulse. Without the horizontal sync pulse, the dc offset on the auto-zero amplifier increases over time (usually about three to five minutes) until it overrides the luminance information. The end result is a slow fade to black or white.
Color Flickering--Asynchronous Operation
Referring to the pin descriptions, the AD720/AD721 uses multiple analog grounds, digital grounds, digital positive supply inputs, analog positive supply inputs, and analog negative supply inputs in order to maximize isolation between analog and digital signal paths. The most sensitive input of the AD720/AD721 is the 4FSC pin: any noise on this pin directly affects the subcarrier and causes degradation of the picture. Digital and analog grounds should be kept separate and brought together at a single point. All power supply pins should be decoupled using 0.1 F ceramic capacitors located as close to the AD720/AD721 as possible. In addition, ferrite beads may be slipped over the power supply leads to reduce high frequency noise. If a high speed RAM-DAC is used (e.g., capable of 80 MHz operation with subnanosecond rise times), care must be taken to properly terminate the input printed-circuit-board traces to the AD720/AD721. Otherwise, ringing on these traces may occur and cause degradation of the picture.
APPLICATIONS HINTS
The AD720/AD721 requires that its 4FSC and composite sync signals be synchronized. In most systems, when the two signals are synchronized, the composite sync signal is generated using a 4FSC signal as the reference. After every four frames, the AD720/AD721 resets the phase quadrature generator. When the CSYNC and 4FSC are synchronized, this reset is transparent to the system because the reference phase does not change. When the CSYNC and 4FSC are not synchronized, the difference between the reference phase and its new value upon reset causes an instantaneous color shift, which appears as a flickering in the color.
Adding NTSC Setup
The easiest way to add the 7.5 IRE unit1 setup is to use a ADV471/478 or ADV477/475 or ADV473 type RAM-DAC, which have a logic-selectable setup (called "pedestal" on some data sheets and "setup" on others).
Color Fidelity
In applying the AD720/AD721, problems may arise due to incorrect input signals. A few common situations follow.
Fade to Black or White--Invalid Horizontal Sync Pulses
A source impedance other than 37.5 (75 75 --a reverse-terminated 75 input) can cause errors in the YUV encoding matrix, which is basically resistive and depends on the correct source impedance for accuracy. Figures 9 and 10 show the correct interface between a RAM-DAC and the AD720 and AD721 respectively, using 75 reverse-terminated connections.
NOTE 1 IRE unit = 7.14 mV.
Some systems produce sync pulses that are longer or shorter than the NTSC and PAL standards specify. The digital sync
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AD720/AD721
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Plastic Leaded Chip Carrier (PLCC) Package P-28A
C1932-7.5-7/94
0.180 (4.57) 0.165 (4.19) 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 5
4
0.056 (1.42) 0.042 (1.07) 26
0.025 (0.63) 0.015 (0.38)
PIN 1 IDENTIFIER
25 0.021 (0.53) 0.013 (0.33) 0.430 (10.92) 0.390 (9.91) 0.032 (0.81) 0.026 (0.66)
0.050 (1.27) BSC
TOP VIEW
11 12 0.020 (0.50) R 0.456 (11.58) SQ 0.450 (11.43) 0.495 (12.57) SQ 0.485 (12.32) 18
19 0.040 (1.01) 0.025 (0.64) 0.110 (2.79) 0.085 (2.16)
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PRINTED IN U.S.A.

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